Modern integrated circuits include features having line widths that are smaller than 100 nm. Efficiently identifying and analyzing defects created during the fabrication of such circuits is an ongoing challenge.
Optical wafer inspection tools, such as KLA-Tencor 2930 Broadband Plasma Defect Inspection System from KLA-Tencor Corporation of Milpitas, Calif., optically examine wafers on which integrated circuits are fabricated. The wafers can be in various stages of processing or can be “deprocessed” to remove layers and expose buried layer. Optical wafer inspection tools illuminate the wafer under test and observe the light from the wafer surface and near subsurface to identify defects. The types of defects that are observable include physical defects on, near, or somewhat below the surface. The wafer inspection tool typically outputs a list of anomalies that may correspond to defects. The list can include a defect category and the positions of the defects in the inspection coordinate system. Defects on the wafer can be identified by comparing the results of the actual scan with the results of a scan of a known good wafer or by comparing the inspection results with a simulated inspection of a known good wafer. In some workflows, equipment after the inspection step is used to perform a mark of some sort on the wafer surface to so that the defect can be found more easily during later processing.
Another type of wafer inspection tool is a scanning electron microscope (SEM) inspection tool such as the Hermes eScan 320XP. An electron beam scans over the surface of the wafer and an image is formed using electrons emitted from the sample in response to the incoming beam. The coordinates of anomalies are noted. The electron beam can form a more highly magnified image of the anomaly. Such SEM-based inspection tools can see both physical defects or electrically related defects, referred to as voltage contrast (VC) defects. In many cases, VC defects or defects that are electrical in nature will be due to a defect that is physically below the wafer surface (i.e., a sub-surface defect).
Defects can also be identified from using other types of wafer inspection tools, such as an optical or thermal system like the ELITE for Semiconductors and probe systems, such as the Hyperion, both of which are available from FEI Company, part of Thermo Fisher Scientific Company, the assignee of the present invention.
Probe systems find defects by electrical probing of exposed conductors on the wafer surface. Defects are identified by electrical signatures from physical probes in contact with the wafer.
The identified defects are often below the surface of the wafer and it is often necessary to expose a buried layer to examine the defects. The coordinates of the defect may be transmitted from the wafer inspection tool to a focused ion beam (FIB) tool and the FIB mills the wafer to expose the defect available for analysis. In some scenarios, the transmission of coordinates might be performed by a factory automation system that coordinates and controls the operation of multiple systems.
To perform the sub-surface evaluation, the FIB may mill a trench in the wafer at the defect coordinates to expose a cross section of a region at the defect site. An image of the exposed cross section can then be viewed using an SEM. In some cases, additional thin slices are removed from the cross section and additional SEM images are formed to provide a series of images through a three-dimensional volume as the exposed wall progresses through the sample. Such a technique is described, for example, in U.S. Pat. No. 9,218,940 to Brogden for “Method and Apparatus for Slice and View Sample Imaging,” which is assigned to the applicant of the present application.
The FIB tool may also be used to prepare a sample from the wafer to be viewed on a transmission electron microscope (TEM), which provides higher resolution than an SEM but which requires a sample that is sufficiently thin for electrons to pass through. As used herein, “TEM” include both a non-scanning TEM and a scanning transmission electron microscope (STEM) and a “TEM image” can include an image formed in either. A method of extracting a thin sample, referred to as a “lamella” from a wafer is described, for example, in U.S. Pat. App. Pub. 2016/0141147 of Brogden et al, for “Automated TEM Sample Preparation,” which is assigned to the assignee of the present application. The extracted sample may be a cross-sectional sample from a plane perpendicular to the surface or a planar-view sample from a plane parallel to the wafer surface. A common feature of all of the described FIB methods is that the FIB is used to assist in some type of sub-surface evaluation at the location of the defect.
The wafer inspection tool provides defect coordinates in a wafer inspection tool coordinate system. To find the defects in the FIB tool, it is necessary to determine the location of the defect in the FIB tool coordinate system. The location of reference points on the wafer are determined in both the wafer inspection tool and in the FIB tool, and then a coordinate transformation system is calculated to transform the coordinates of the defects as determined in the wafer inspection tool to coordinate in the FIB tool. Reference points can include, for example, notches or flat regions in the wafer circumference, as well as marks produced on the wafer during the fabrication process or marks made specifically for alignment.
Modern integrated circuits can have transistors fabricated in array with a pitch of 50 nm or even smaller. To capture a transistor gate in a lamella as thin as 10 to 15 nm lamella requires precise positioning of the FIB beam to fabricate the lamella. In many cases, it is desirable to perform FIB milling with positional accuracy errors less than a few nanometers. This process of using the defect coordinates generated by the wafer inspection tool to position the focused ion beam for preparing an inspection site is inexact. The resolution of the optical inspection system is limited by the wavelength of the light used, and may not be sufficient to prepare the cross section or sample for viewing. Also, the mapping of the wafer inspection tool coordinate system to the FIB tool coordinate system may be inexact.
Typically, a cross section or lamella is prepared at the defect location determined by the coordinate transformation as part of the FIB processing. In practice, that location often misses the actual defect and so will not result in an image of the defect, depriving the process engineer of needed information.